1. Field of the Invention
The present invention relates to a semiconductor storage device for rewritably storing data to each of unit blocks into which a memory cell array is divided. Particularly, the present invention relates to a semiconductor storage device having a configuration in which a row of sense amplifiers including a plurality of sense amplifiers is used each a cache memory.
2. Description of the Related Art
As a general configuration of a semiconductor storage device such as DRAM, such a configuration in which a memory cell array is divided into a plurality of banks and each bank is further divided into a plurality of unit blocks has been well known. Data is stored and held in memory cells formed at intersections between a plurality of word lines and a plurality of bit lines in each unit block. In conventional DRAM, a row of sense amplifiers including a plurality of sense amplifiers is arranged on each of both sides of the unit block. A configuration in which switches are provided between the unit block and the row of sense amplifiers has been also proposed (see, for example, Japanese Patent Laid-Open No. 2004-103657). If the configuration in which the row of sense amplifiers is arranged on each unit block is employed, data read out from the memory cells is held in the row of sense amplifiers by selectively activating an arbitrary word line. Thus, the row of sense amplifiers of each unit block can be used as a cash memory (hereinafter referred to as sense amplifiers cash).
Generally, refresh operation needs to be performed at a predetermined time interval in order to hold data stored in DRAM. This refresh operation is so controlled that after bit lines connected to the row of sense amplifiers is pre-charged, a word line selected to be refreshed is activated, data on the bit lines read out from memory cells on a selected word line is amplified by the sense amplifiers and rewritten into the memory cells. Then, if the refresh operation of the unit block connected to a row of sense amplifiers used as a sense amplifiers cache is performed, data held in the row of sense amplifiers at that time is destroyed in the pre-charge prior to the refresh operation. Therefore, a time in which data can be held in the sense amplifiers cache is under restriction of a refresh interval. Usually, in DRAM, data in the sense amplifiers cache needs to be updated each time a refresh takes place because the refresh operation is performed by selecting the word line in succession at a short interval of some micro seconds. As a consequence, the sense amplifiers cache cannot be used effectively, and cache hit rate drops, which is a problem to be solved.